Modeling and synthesis of the network in distributed embedded systems

Design of distributed embedded systems is a novel challenging task and it requires to raise the level of abstraction to overcome the complexity of the design. In particular, modeling languages and custom profiles are necessary to address network specification at this level of the abstraction. In order to verify the NW design model and reach the actual implementation, model manipulation and code generation are needed not only for simulation and performance analysis of the design model but also to refine the model and reduce the level of abstraction. In this work, I propose the use of UML diagrams combined with a formal computational model as a key solution to generate code, solve the NW design problem and manipulate each solution to generate different NW alternatives. This thesis proposes a formal framework to capture the application requirements, library of network components, environment description and the rules to compose them. The framework generates code for design verification by simulation and provides back annotation mechanism of the simulation results to refine the original model. The resulting code is used in the final implementation of the network. Moreover, the framework abstracts existing RTL IPs into UML for component reuse. This thesis presentation is organized as follows. Section I gives an overview about network synthesis and the problems to be solved, while Section II describes the proposed methodology to solve such problems. Section III reports the progress done as well as the current and future work.